1. Field of the Invention
The present invention relates to a method for fabricating a vertical bipolar junction transistor, and more particularly, to a method for forming a contact region of a vertical bipolar junction transistor by a self-aligned silicidation process (salicide).
2. Description of the Prior Art
Bipolar junction transistors are important elements of a semiconductor. In general, there are two types of bipolar junction transistors: a lateral bipolar junction transistor and a vertical bipolar junction transistor.
FIG. 1 shows a method for fabricating a vertical bipolar junction transistor according to the prior art. Referring to FIG. 1, a vertical bipolar transistor is shown on a semiconductor wafer 100 having a P-type substrate 110. An N-type buried layer 113 is formed on an upper portion of the P-type substrate 110. A P-type epitaxial layer 115 functioning as a collector region of the vertical bipolar junction transistor has been grown on the P-type substrate 110 having the N-type buried layer 113. At least one N-type sink 116 is formed in the epitaxial layer 115 from the top surface of the epitaxial layer 115 to N-type buried layer 113 so that the N-type sink 116 can separate the elements of the vertical bipolar transistor in the horizontal direction by defining a P-type well 117 in the epitaxial layer 115. A base mask 119 is formed with an opening 121 to expose a portion of the P-type well 117 in the epitaxial layer 115 for defining a base pattern of the vertical bipolar junction transistor.
The epitaxial layer 115 has a P-type collector enhancement region 123 formed by implanting impurities above the N-type buried layer 113 through the opening 121 and an N-type base region 125 is formed by implanting impurities above the P-type collector enhancement region 123 through the opening 121. Then, a polysilicon emitter contact region 127 is formed on the surface of the N-type base region 125. A P-type emitter region 129 is formed below the emitter contact region 127 and in an upper portion of the surface of the N-type base region 125. Furthermore, an N-type base contact region 131 is formed in an upper portion of the surface of the N-type base region 125. A plurality of collector contact regions 133 and 134 are formed in upper portions of the surface of the P-type well 117 except the portion where the base region 125 is formed.
However, the epitaxial layer of the vertical bipolar junction transistor used for the collector region according to the prior art is normally a thin epitaxial layer 115. In the prior art method for fabricating a vertical bipolar junction transistor, it is necessary to perform many doping processes and thermal processes through the opening 121 in order to cause the multi-lever structures including the collector enhancement region 123, the base region 125, the emitter region 129, the base contact region 131, and so on formed respectively in the epitaxial layer 115. Thus, precisely controlling the position of the multi-lever structures such as the collector enhancement region 123, the base region 125, the emitter region 129, the base contact region 131, and so on in the epitaxial layer 115 having limited width and depth is difficult. Furthermore, precisely controlling the concentration of implanted impurities in the above-mentioned multi-lever structures is also difficult after many thermal processes so that the electrical performance of the vertical bipolar junction transistor is greatly affected.